Moore's Law is not over yet. According to reports, due to the recent impact of the epidemic, the Japanese ITF recently held an online press conference in Tokyo, Japan on November 18.
Luc Van den hove, CEO and President of IMEC, gave a keynote speech and introduced the company’s research overview. He emphasized that through close cooperation with ASML, the next generation of high-resolution EUV lithography technology-high NA EUV lithography technology commercialize. IMEC emphasizes that it will continue to reduce the process scale to 1nm and below.
Many semiconductor companies, including Japan, have withdrawn from process miniaturization, claiming that Moore's Law has come to an end. In other words, water is unprofitable because the manufacturing cost is too expensive.
While many Japanese lithography tool manufacturers have withdrawn from the EUV lithography development stage, semiconductor research institutes IMEC and ASML have been cooperating to develop EUV lithography technology, and EUV lithography technology is very important for ultra-fine scales.
At ITF Japan 2020, IMEC proposed a roadmap for miniaturization of logic devices of 3nm, 2nm, 1.5nm and below 1nm.
The PP marked under the name of the upstream technology node is the pitch (nm) of the polysilicon interconnection line, and MP is the wiring pitch (nm) of the fine metal. It should be noted that the past technology node refers to the minimum processing size or gate length, but now it is just a "tag" and does not refer to the physical length of a certain location.
The structures and materials introduced here, such as BPR, CFET, and channels using two-dimensional materials, have been published separately.
According to TSMC and Samsung Electronics, starting from the 7nm process, some processes have introduced EUV lithography equipment with NA=0.33. The 5nm process has also achieved an increase in frequency, but for ultra-fine processes after 2nm, higher resolution is required. Rate and higher NA of lithography equipment (NA=0.55).
According to IMEC, ASML has completed the basic design of the high NA EUV exposure system as the NXE:5000 series, but the commercialization is planned around 2022. This next-generation system will become very tall due to its huge optical system, and it is likely to stand under the ceiling of a traditional clean room.
ASML has been working closely with IMEC in the past to develop lithography technology, but in order to develop lithography processes using high NA EUV lithography tools, a new "IMEC-ASML High NA EUV Laboratory" was established in the IMEC campus to promote joint Develop and develop lithography process using high NA EUV lithography tools. The company also plans to work with material suppliers to develop more efficient products such as masks and resists.
Van den hove finally said: "The purpose of miniaturization of logic device technology is to reduce power consumption, improve performance, reduce area, and reduce cost, which is commonly referred to as PPAC. In addition to these four goals, as the miniaturization moves toward 3nm, 2nm, 1.5nm, and even beyond 1nm to reach sub-1nm, we will strive to achieve environmentally friendly microprocessors that are suitable for a sustainable society." He said that he will continue to work on process miniaturization and show great enthusiasm.
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