After the large-scale production of TSMC’s 5nm process, TSMC’s next-generation major chip process technology, 3nm, is currently being promoted as planned. It is planned to start risky trial production in 2021 and mass production in the second half of 2022.
It is reported that TSMC’s 3nm process has prepared 4 waves of production capacity, most of which will be left to their major customer Apple.
In terms of production capacity, TSMC is currently advancing the 3nm process as planned and put into mass production in the second half of 2022, with a set production capacity of 55,000 wafers per month. However, 55,000 wafers are the monthly production capacity at the initial stage of production, and will gradually increase thereafter, and the monthly production capacity will increase to 100,000 wafers in 2023.
Before that, whether it was 7nm or 5nm, Huawei was one of TSMC’s most important customers. 3nm was the first TSMC advanced process that Huawei had absent in recent years.
It is reported that TSMC's 7nm technology was officially put into mass production in April 2018. According to the data, the first batch of TSMC’s 7nm products include Bitmain’s mining chips, Xilinx FPGA chips, Apple A12, Huawei Kirin 980, etc. The only customers of TSMC’s 5nm are Apple and Huawei. Among them, Huawei’s order for TSMC is 15 million. However, due to the limited production time, the order was only completed about 60% before the production was stopped, and Apple monopolized TSMC’s 5nm. Capacity.
Core Things reported on August 25 that at TSMC’s 26th Technical Symposium, TSMC revealed more details of its 3nm process node, and shared the relevant progress of the 5nm follow-up products N5P and N4 process nodes.
TSMC has been leading the way in advanced manufacturing processes. 3nm technology is planned to enter risk production in 2021 and mass production in 2022. Intel's 7nm is expected to be launched until the end of 2022 at the earliest.
According to reports, compared with the 5nm N5 process, under the same power consumption, TSMC’s 3nm N3 performance can be improved by 10-15%; under the same performance, N3 power consumption can be reduced by 25-30%; the logic density, SRAM density, and analog density of N3 are respectively It is 1.7 times, 1.2 times, 1.1 times that of N5.
At the same time, TSMC President Wei Zhejia announced that TSMC has integrated its 3D packaging technology platforms including SoIC, InFO, CoWoS, and named it TSMC 3D Fabric.
TSMC’s senior vice presidents Kevin Zhang and YP Chin mentioned in a pre-recorded video that TSMC is building a new R&D center next to its headquarters that focuses on 2nm chip research and development. It has 8,000 engineers and will operate an advanced production line. The project The first phase will be completed in 2021.
As the “number one player” of global foundry, from TSMC’s sharing, we can see the trend of the most cutting-edge chip manufacturing technology in the world's advanced manufacturing process.
It is reported that TSMC's 5nm N5 process has widely adopted EUV technology. Compared with the 7nm N7 process, the performance of the TSMC N5 process under the same power consumption has increased by 15%, the power consumption under the same performance has been reduced by 30%, and the logic density is 1.8 times that of N7.
TSMC also mentioned that the defect density learning curve of N5 is faster than that of N7, which means that the 5nm process will reach a higher yield faster than its previous node.
N5P is mainly for high-performance applications and is planned to be put into use in 2021. Compared with N5, under the same power consumption, the performance of N5P can be increased by 5%; under the same performance, the power consumption of N5P can be reduced by 10%.
Because it is compatible with the N5 node on IP, TSMC’s 5nm N4 process can provide direct migration with enhanced performance, power consumption and density. TSMC plans to start N4 risk production in the fourth quarter of 2021, and the goal is to achieve mass production in 2022.
Compared with the 5nm N5 node, the performance of TSMC’s 3nm N3 under the same power consumption can be increased by 10-15%, and the power consumption under the same performance can be reduced by 25-30%; the logic density is increased by 70%, and the SRAM density is increased by 20%. The density is increased by 10%.
In addition, TSMC also introduced the N12e process designed for low-power devices such as IoT, mobile and edge devices. This process is an enhanced version of TSMC’s 12 nm FinFET node with lower power consumption, higher performance, and ultra-low power consumption. Leakage devices and ultra-low Vdd design as low as 0.4V.
Recently, the battlefield of advanced manufacturing can be described as ups and downs. Intel's process evolution has once again skipped votes. Samsung frequently reports that the yield rate is not enough. Only TSMC has continued to have good news. Not only has its stock price continued to soar, it has become the world's tenth largest company by market value, but also ushered in manufacturing. A new milestone of 1 billion 7nm chips.
From the moment that 7nm was first completed, TSMC has become the hope of the entire "global village". Except for IDM giants such as Samsung and Intel with their own advanced manufacturing plants, most of the head chip design companies have lined up outside the 7nm gate of TSMC.
There is no other reason. The more advanced the process technology, the higher the chip performance and the lower the power consumption, the more competitive it is in the market.
TSMC not only rushes fast, but also has a high yield rate. In 2018, more than 50 7nm chips were mass-produced, and the foundries were TSMC. In 2019, there are more than 100 types of 7nm chip designs manufactured by TSMC. Chip giants such as Apple, Qualcomm, Huawei, Nvidia, AMD, Xilinx, and MediaTek are all customers of TSMC's 7nm.
At the same time, TSMC’s 7nm N7+ process is the world’s first node to adopt EUV in mass production, and the backward-compatible N6 logic density has increased by 18%. According to TSMC, N6 has the same defect density as N7.
TSMC’s 2019 annual report shows that this year, TSMC produced 10,761 different chips for 499 customers, and its market share in the semiconductor manufacturing field reached 52%.
Judging from the revenue of the world's top foundries in the first half of 2020, TSMC's revenue exceeds the total revenue of 2-9 foundries.
According to Taiwanese media reports, Taiwan’s three major science parks have a turnover of NT$1.3681 billion (approximately RMB 322 billion) in the first half of 2020, of which nearly 41% is contributed by TSMC.
According to data from Gartner, an international IT research and consulting company, advanced manufacturing processes will contribute a higher and higher proportion of revenue to the foundry market.
TSMC, which dominates half of the foundry industry, is it possible to be overtaken in a curve?
TSMC founder Zhang Zhongmou is very humble. In an interview with the media in early 2020, he mentioned that Samsung Electronics is a very powerful opponent. TSMC currently has the advantage, but the war between TSMC and Samsung is definitely not over, and TSMC has not won.
Compared with Samsung, TSMC has many advantages. For example, it is a pure foundry. Compared with IDM manufacturers such as Samsung, which has its own chip design business, it is easier to gain the trust of customers; for example, its technology advances smoothly and continues to take the lead in 7nm. After the market, it will soon usher in the large-scale implementation of 5nm.
TSMC President Wei Zhejia once revealed that the number of tape-out chips completed with TSMC’s 5nm will be higher than the same period in the initial stage of 7nm mass production. 5nm will also become another major and long-life process node of TSMC after 7nm. It is estimated that 5nm will account for 10% of revenue in 2020.
But the core bargaining chip to win the market-technological leadership-still has variables.
Samsung, which has lost the 7nm market, is already in a position to win the battle against the next 5nm and more advanced processes.
The next battle is very clear, the core actions are to spend money, expand production, and take the lead.
First, continue to increase R&D investment and capital expenditure.
As early as 2017, TSMC revealed that it planned to invest US$20 billion in a 3nm process chip factory. According to financial report data, TSMC’s R&D investment in 2019 was nearly US$3 billion, accounting for approximately 8.5% of its annual revenue; its capital expenditure in 2020 is expected to reach US$16 billion to US$17 billion.
TSMC is also building a new R&D center with 8,000 engineers next to its headquarters. The first phase of the project will be completed in 2021 and plans to develop 2nm chips.
Samsung has announced huge spending plans one after another. In April 2019, Samsung announced plans to invest a total of 133 trillion won (approximately US$116 billion) in LSI and foundry industries in the next ten years. In October of the same year, Samsung spent $2.5 billion to purchase 15 EUV lithography machines from ASML. In January 2020, Samsung spent US$3.38 billion to place an order of 20 EUV lithography machines with the lithography machine hegemon ASML. In addition to the planned use of 7nm, 5nm and other logic chips, it also plans to be used in the production of DRAM memory chips.
Secondly, steadily expand the production line.
TSMC said it is expanding its N5 production of Fab 18 at its first 5nm fab. Fab 18 will begin mass production of N5 in the second quarter of 2020, aiming to process approximately 1 million 12-inch wafers per year.
Prior to this in May 2020, TSMC and Samsung respectively announced plans to build new 5nm fabs.
TSMC’s new semiconductor factory project in Arizona, USA, will start with 5nm technology and have a monthly capacity of 20,000 wafers. It is planned to be completed and put into production in 2024.
Samsung will build a new 5nm fab in Pyeongtaek, south of Seoul, and is expected to start production in the second half of 2021. The products are mainly used for 5G networks and high-performance computing.
Most importantly, seize the 5nm market and surpass 3nm R&D.
In the second half of this year, Huawei's Kirin 1020 processor and Apple A14 processor using TSMC's 5nm technology will enter the market. Ampere Computing also manufactures its next-generation server chips based on the N5 process. Other chip giants reported to have placed orders with TSMC for 5nm include Qualcomm, AMD, MediaTek, and NXP.
At the end of July 2020, Samsung Electronics stated that its chip foundry business had achieved record quarterly and semi-annual revenues due to the increase in customer inventories. It also revealed that it has begun mass production of 5nm chips and is developing 4nm processes. According to Samsung's original plan, it will start mass production of Samsung's 5nm Exynos chips from August 2020. Qualcomm, Google, etc. are currently announced to adopt Samsung's 5nm process. However, there have been reports recently that Samsung has encountered problems with the yield of the 5nm EUV process.
In the more advanced 3nm process, Samsung took the lead in adopting the breakthrough GAA surround gate transistor technology to create higher-density chips.
TSMC 3nm will continue to use the FinFET transistor architecture, and will not upgrade to GAA technology until the second generation of 3nm or 2nm.
At today’s TSMC Technology Symposium, TSMC shared some industry developments that can surpass 3nm, such as nanosheet, nanowire and other technologies, as well as new materials such as high mobility channels, 2D transistors and carbon nanotubes, but it did not provide Details of the technology used.
TSMC has been deeply involved in nanosheet technology for more than 15 years and has proven that it can produce 32Mb nanosheet SRAM devices that work at 0.46V. TSMC has also identified several non-silicon materials suitable for 2D, which can control the channel thickness below 1nm. In addition, TSMC is also studying carbon nanotubes, a new type of substrate.
At the same time, both TSMC and Samsung are accelerating the development of more advanced packaging technologies.
7nm, 5nm, 3nm, 2nm... As the advanced process node gradually approaches zero, new problems are facing advanced chip manufacturers.
On the one hand, some people in the industry have begun to explore whether there is a more scientific and reasonable nomenclature to replace the existing chip manufacturing process naming logic.
On the other hand, not all chips need to pursue the most advanced process technology. Chip scaling certainly helps to improve performance, but as chip manufacturing processes continue to approach physical limits, costs are getting higher and higher, and gains are decreasing. The overall cost performance may not be competitive.
Of course, no matter how uncertain the way forward, advanced manufacturing processes will still be the battlefield for the three giants, TSMC, Samsung and Intel, to compete for the most advanced technology. Perhaps SMIC will still be the entrant in the future.