CY7C68013A overview

The USB interface has the advantages of fast speed and low cost, and has become a necessary interface on modern computers. The theoretical speed of the USB2.0 HIGH-SPEED interface is 480Mbit/S, and the actual bandwidth used is above 200M. In some occasions where reliability and real-time requirements are not particularly high, the easy-to-use and easy-to-use characteristics of USB make it the best Communication interface selection. Cypress EZ-USB®FX2LP™ (CY7C68013A/14A) is a highly integrated, low-power USB 2.0 microcontroller. Its interface rate can reach 96Mbytes/s, and the cost is only more than ten yuan RMB.

CY7C68013A(FX2LP) is connected with FPGA

We use the USB interface in some customized devices. The most mainstream USB peripheral interface chip on the market is Cypress's CY7C68013A. In order to achieve high-bandwidth communication, CY7C68013 needs to work in GPIF or SLAVE FIFO mode. The two modes are not very clear. Based on our existing experience, we will briefly explain the two modes:

The GPIF mode is suitable for CY7C68013 to actively communicate with the external chip. GPIF realizes the conversion of the state machine through several control signals, thereby generating different timings. This mode can be used in external SRAM, CMOS SENSOR, CPU, DSP and other occasions, where DSP and CPU work in slave mode;

The SLAVE FIFO mode is suitable for use with chips that can run state machines, such as FPGAs.

When using CY7C68013 to communicate with FPGA, the SLAVE FIFO mode is generally used. Chapter 9 of EZ-USB_TRM2 describes the SLAVE FIFO mode in detail. There are a total of 4 endpoints in CY7C68013, and each endpoint can receive or send. The corresponding SLAVE FIFO has 2 address lines to select the corresponding endpoint buffer.

A very important setting for SLAVE FIFO is the clock setting. It can work in asynchronous or synchronous mode. In actual use, synchronous mode is recommended. In order to reduce costs, you can use the 48Mhz clock generated by CY7C68013 itself. For detailed setting instructions, see Fig.9 -6. The SLAVE FIFO has 4 flag pins to indicate the FIFO status (empty, half full, full, custom, etc.). These pins are needed when writing the state machine in the FPGA. Pay special attention to the FLAGD pin. It can be used as a chip select for SLAVE FIFO. This function is needed when there is more than one device on the bus, and it can be ignored at other times. The other pins and standard FIFO are nothing special, you can understand at a glance. After the CY7C68013 is initialized with the 51 program, the communication between the computer and the FPGA can be opened up. If multiple endpoints are used, it is necessary to pay attention to an effective scheduling algorithm on the FPGA to avoid the delay in fetching the data in a certain endpoint buffer and cause communication errors.